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High-Performance IP Integration Specialist

2 months ago

San Jose, California, United States Microchip Technology Full time
Job Description:

Company Overview: Microchip Technology is a leading provider of low-power and highly-reliable field-programmable gate arrays (FPGAs). Our FPGAs are used in a wide variety of applications, including embedded vision, digital signal processing, machine learning, industrial and medical equipment, and satellites.

Job Summary: We are seeking a highly skilled and experienced System Interconnect Architect to join our dynamic team. The successful candidate will be responsible for leading cross-functional teams to deliver high-performance IP integrations into our FPGA products, that meet market & customer requirements across a broad range of application spaces.

Key Responsibilities:

  • Lead cross-functional teams to deliver high-performance IP integrations into Microchip FPGA products
  • Work on ASIC & FPGA IP development, integration, and deployment for System Interconnect such as PCIe, CXL, DDR, NOC, High Speed Serial Transceivers, High Performance Parallel IO interfaces
  • Understand customer use models and the role of IP in overall system architecture
  • Work cross-functionally with other architects, designers, and back-end implementation teams
  • Lead and manage other engineers in the team

Requirements/Qualifications:

  • MS or higher in EE, CS, CE or other applicable disciplines
  • 12+ years of relevant experience
  • Proven experience in ASIC & FPGA IP development, integration, and deployment, including all stages of development from Synthesis, constraint management, place & route, floor planning, timing closure, CDC/RDC
  • Knowledge and experience with system-level performance modeling in TLM/SystemC/Other will be an advantage
  • Experience in technical leadership and people management will be an advantage
  • Proven ability to work cross-functionally with other architects, designers, and back-end implementation teams
  • Knowledge and experience with Synopsys & Cadence ASIC flows
  • Scripting for EDA in Perl, Python, Tcl will be an advantage

Work Environment:

  • 0% - 25% travel time
  • 80% sitting, 10% standing, 10% walking; 100% indoors; Usual Business Hours

Compensation and Benefits:

  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments.
  • In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.