Senior CPU Subsystem Design Engineer
1 week ago
In this role, you will be responsible for designing and developing CPU subsystems for Intel's cutting-edge SoC designs. As a Senior CPU Subsystem Design Engineer, you will work closely with cross-functional teams to develop and integrate logic design, register transfer level (RTL) coding, and simulation for SoC designs.
You will participate in the definition of architecture and microarchitecture features of the block being designed, perform quality checks in various logic design aspects, and apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals.
Additionally, you will review the verification plan and implementation to ensure design features are verified correctly, resolve and implement corrective measures for failing RTL tests, and follow secure development practices to address the security threat model and security objects within the design.
Responsibilities- Develops logic design, RTL coding, and simulation for SoC designs
- Integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design
- Participates in the definition of architecture and microarchitecture features of the block being designed
- Performs quality checks in various logic design aspects
- Applies various strategies, tools, and methods to write RTL and optimize logic
- Reviews the verification plan and implementation to ensure design features are verified correctly
- Resolves and implements corrective measures for failing RTL tests
- Follows secure development practices to address the security threat model and security objects within the design
- Bachelor's degree in computer engineering, electrical engineering, or related field
- 10+ years of relevant experience in CPU based SoC designs, processor based SoC architectures, NoC design, and integration with AMBA interconnect protocols
- Experience with RTL development using ASIC development techniques and designs flows at modern technology nodes
- Experience in designing clock circuitry, debug, security, low power methodologies at the SoC level
- Digital design experience
- Experience with scripting languages (e.g., Python or Perl)
- Master's degree in computer engineering, electrical engineering, or related field
- 6+ years of experience in digital design involving multiple clock domains and clock, power management, low power design, tools, and methodologies
- Experience with Ethernet, PCIe, or TSN
This role will be eligible for Intel's hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site.
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