Senior CPU Subsystem Architect

2 days ago

San Jose, California, United States Intel Full time
Job Summary

We are seeking a highly skilled CPU Subsystem Design Engineer to join our team at Intel. As a key member of our Programmable Solutions Group, you will be responsible for designing and developing cutting-edge CPU subsystems that meet the highest standards of performance, power efficiency, and reliability.

Key Responsibilities
  • Develop and implement logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating logic of IP blocks and subsystems into a full chip SoC or discrete component design.
  • Participate in the definition of architecture and microarchitecture features of the block being designed, ensuring alignment with business goals and technical requirements.
  • Perform quality checks in various logic design aspects, from RTL to timing/power convergence, to ensure design integrity and meet power, performance, area, and timing goals.
  • Apply various strategies, tools, and methods to write RTL and optimize logic, ensuring design meets power, performance, area, and timing goals, as well as design integrity for physical implementation.
  • Review and implement verification plans and implementations to ensure design features are verified correctly, resolving and implementing corrective measures for failing RTL tests to ensure correctness of features.
  • Follow secure development practices to address security threat models and security objects within the design, working with IP providers to integrate and validate IPs at the SoC level.
  • Drive quality assurance compliance for smooth IPSoC handoff, working with Physical Design teams to synthesize RTL blocks and provide estimates of timing, area, and power.
Requirements
  • Bachelor's degree in computer engineering, electrical engineering, or related field.
  • 10+ years of relevant experience in CPU-based SoC designs, processor-based SoC architectures, NoC design, and integration with AMBA interconnect protocols.
  • Experience with RTL development using ASIC development techniques and design flows at modern technology nodes, including synthesis and timing closure.
  • Experience in designing clock circuitry, debug, security, low power methodologies at the SoC level, digital design, and scripting languages (e.g., Python or Perl).
Preferred Requirements
  • Master's degree in computer engineering, electrical engineering, or related field.
  • 6+ years of experience in digital design involving multiple clock domains and clock, power management, low power design, tools, and methodologies, power intent UPF specifications, Ethernet, PCIe, or TSN.
What We Offer

We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock, bonuses, and benefit programs, including health, retirement, and vacation.

Salary range dependent on a number of factors, including location and experience.

This role will be eligible for our hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site.

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