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CPU Design Engineering Manager
2 months ago
In the context of Intel GmbH, this position is associated with the company's standalone business strategy and is expected to fully transition to a standalone company at some point in the future. The successful incumbent in this role will manage a team responsible for designing CPU subsystems that are used by customers to run workloads and program other IPs. The CPU subsystems team designs and implements a wide range of IPs, including CPUs and interconnects.
The successful incumbent in this position will perform the following key responsibilities:
- Leads and manages CPU silicon design teams within one or more areas of functional development, including logic design, verification, circuit design, and/or physical design for a CPU.
- Manages the engineering team resources, their functions, activities, responsibilities, and drives continuous improvement and silicon quality standards.
- Takes an active part in defining CPU microarchitectural features and drives their implementation.
- Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements.
- Works to continuously improve CPU silicon development processes and architecture definition across areas of CPU silicon design.
- Oversees and reviews design verification test results, data analysis, issue tracking, root cause analysis, and drives corrective actions implementation for silicon design.
- Works closely across other IP and SoC development teams that integrate the CPU to design complex projects, ensure quality, drive performance, and design implementation.
- Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
- Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.
- Provides daily technical guidance to the team to implement designs in RTL and execute design flow to tape out designs to meet schedules.
- Resolves conflicts.
- Manages the design team in cross-functional meetings, prepares team status, and manages hiring.
Education Requirements
A Bachelor's degree in electrical engineering or a related field.
Minimum Qualifications
- 10+ years of experience in CPU architecture and design for ARM and CPU subsystems, including cache architecture and coherency.
- Programming model of peripheral IPs such as USB, Ethernet, I3C, PCIe.
- Coherent and non-coherent Network-on-Chip architecture and design.
- CPU subsystems integration challenges and tradeoffs for power, performance, and area.
Preferred Qualifications
A Master's degree with 6+ years or a PhD with 4+ years in electrical engineering or a related field.
6+ years of experience in any of the following:
- ASIC flow from RTL to GDSII with synthesis, place and route, physical implementation, constraint design, timing closure, DRC/LVS, DFT, DFD, memory designs, clock reset circuits, low power modes, packaging tradeoffs.
Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experienceWorking ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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