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Senior ASIC Design Engineer
2 months ago
Job Title: Senior ASIC Design Engineer - RTL, PCIe, CXL
Job Type: Full-time
Location: Remote (CyberCoders)
Job Description:
We are a leading provider of high-performance interconnect solutions for data centers and HPC, and we're looking for a Senior ASIC Design Engineer to join our team. As a key member of our design team, you will be responsible for designing and developing high-performance ASICs for cloud computing applications.
Key Responsibilities:
- Participate in architecture definition and modeling
- Contribute to micro-architecture specification and reviews
- Review industry standard specs and ensure IPs are kept up to date for compliance
- Define design partitioning for efficient IP/sub-system/full chip implementation
- Review and provide feedback on verification plans and methodology
- Drive block/chip/system level development and execution
- Work with Hard IP designers, verification, validation, Firmware engineers, and architects to produce thoroughly verified, robust IP
- Actively participate in post-silicon bring-up, validation and compliance testing
Requirements:
- Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar
- Years of experience in logic design using Verilog/System Verilog
- Very strong domain knowledge about PCIe/CXL
- Proven track record of taking several chips in from product definition to production
- Experience in complex ASIC design
- Good understanding of ASIC design and verification methodologies and flows
- Architecture/Micro-architecture definition
- Design partitioning and Hard IP interactions
- Multiple async clock domain designs
- Design for test
- Clock/Reset
- Power-aware
- Excellent understanding of Synthesis, STA, CDC, Lint, LEC
- Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
- Proficient in Perl scripting
Preferred Skills:
- ASIC Design
- RTL Design
- Microarchitecture
- PCIe
- CXL
- UART
- I2C
- SPI Flash
- Verilog
- System Verilog