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Lead FPGA Design Engineer
2 months ago
Ouster is a leading technology company that specializes in developing innovative sensors and tools for engineers, roboticists, and researchers. We are seeking a highly skilled and experienced digital hardware FPGA/ASIC design and verification engineering lead to join our Firmware team.
Key Responsibilities- Lead and perform safety analysis of FPGA subsystems to ensure compliance with industry standards and regulations.
- Develop and implement functional safety documentation, including V model requirements and FMEDA analysis, to ensure the reliability and robustness of our designs.
- Define, develop, and integrate features across our FPGA stack with a focus on functional safety and reliability, ensuring seamless hardware and software integration.
- Enforce and refine FPGA development processes to support functional safety needs, ensuring efficient and effective design implementation.
- Perform hands-on work using laboratory tools for board bring-up and troubleshooting, ensuring timely and accurate issue resolution.
- Develop automation scripts for repetitive tasks to facilitate efficiency and reliability, reducing manual errors and increasing productivity.
- Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field.
- At least 5 years of experience in FPGA development, including HDL code development, simulation, test bench development, synthesis, and timing closure.
- Experience and understanding of safety concepts and industry standards, including ISO 26262 and ASIL-B.
- Highly proficient in RTL development using Verilog and SystemVerilog.
- Proficient in scripting languages such as Python, TCL, Perl, and bash.
- Experience with embedded system development in CPU and FPGA-based devices, including Xilinx Zynq and Intel Arria devices.
- Experience with Xilinx and/or Intel FPGA toolchains.
- Experience with DSP algorithm implementations in FPGAs.
- Experience with processor architectures and various communications protocols, including DDR4, AXI, I2C, UART, SPI, and Ethernet.
- Familiarity with High-Level Synthesis (HLS) and best practices with version control technologies such as Git.
- Proficient in C or C++ programming language.
- Familiarity with leading verification methodologies, including UVM.
Ouster offers a competitive compensation package, including a base salary of $190,000-$250,000 per year, dependent on skills, work experience, location, and qualifications. This role may also be eligible for equity and benefits. We prioritize the well-being of our employees and offer a range of benefits, including 15 vacation days, 10 paid holidays, paid parental leave, pre-tax commuter or health care/dependent care accounts, 401K match, medical, vision, and dental plans, life insurance, and short-term disability and long-term disability.
Ouster is an Equal Employment Opportunity employer that pursues and hires a diverse workforce. We prohibit harassment of any kind and strive for a healthy and safe workplace. Pursuant to the San Francisco Fair Chance Ordinance, Ouster considers qualified applicants with arrest and conviction records for employment. If you have a disability or special need that requires accommodation, please let us know.
