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Design Verification Engineer

2 months ago

Beaverton, Oregon, United States Apple Full time
Job Title: Design Verification Engineer

At Apple, we are seeking a highly skilled Design Verification Engineer to join our dynamic team. As a key member of our hardware engineering group, you will play a critical role in ensuring the quality and reliability of our products.

Key Responsibilities:
  • Develop and execute verification plans for IP designs, including test-plan development, verification environment development, and test-writing.
  • Collaborate with cross-functional teams to ensure bug-free first silicon for our products.
  • Design and develop verification environments, including stimulus, checkers, assertions, trackers, and coverage.
  • Develop and maintain detailed test and coverage plans based on micro-architecture.
  • Execute verification plans, including design bring-up, DV environment bring-up, regression enabling, and debug of test failures.
Requirements:
  • BS degree in technical discipline with minimum 3 years of confirmed experience.
  • Deep proven understanding of SystemVerilog test-bench language and UVM.
  • Shown experience developing scalable and portable test-benches.
  • Validated experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate level simulations.
  • Experience with IP verification methodology.
  • Solid understanding of UVM knowledge, C/C++ knowledge, and scripting languages such as Python, Perl, or TCL.
  • Deep knowledge of formal verification methodology.
Preferred Qualifications:
  • Experience with DDR PHY or Controller.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.