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Senior SOC Design Verification Engineer
2 months ago
Tesla's Autopilot AI (Dojo) Silicon Development Team is seeking a highly skilled Design Verification Engineer to develop and manage the verification and test environments for state-of-the-art chip designs. As a key member of our team, you will work with talented engineers to advance Tesla's AI mission and solve challenging problems.
Key Responsibilities
Define and review verification and validation test plans at both the unit level and SOC level. Review and aid in developing the RTL design architecture and specification. Verify design functionality through writing reusable and scalable testbenches, scoreboards, assertions, and assembly tests. Execute coverage of various use cases, then feeding back to the test plans for closure. Integrate different IPs onto the SOC testbenches, then perform full-chip/cluster/integration level testing. Integrate and work with VIPs to stress-test our IPs for various protocols. Develop and maintain regressions, tools, infrastructure, and methodology. Functional bringup and debug on various platforms and tools. Run real-world software use cases on emulation and FPGA. Measure performance and feedback to designers. Post-silicon validation bringup and production ramp.
Requirements
BS or MS in computer science, computer engineering, or electrical engineering. 5+ years of work experience in designing, verifying, and validating complex hardware systems. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging SOC, CPU, GPU, fabric, NOC, memory, various protocols like PCIe or Ethernet, or other complex ASIC designs. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases. Experience with design verification and validation methodologies and strategies. Experience with power and performance modeling concepts. Good communication skills, and a team player. Able to work independently in a fast-paced team and environment.
Desirable Experiences
Deep knowledge of system architecture including CPU, GPU, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), PCIe, Ethernet, DMA, CSRs, etc. Experience with hardware-software interaction, and software application testing on the chip. Experience with system coherency verification. Experience with boot, reset, clock, and power management verification. Experience with integrating IPs onto the chip. Prior work experience with vendors is a plus. Emulation/FPGA experience is a plus. Post-silicon bringup and validation experience is a plus.
