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Design Verification Specialist
2 months ago
PDDN INC. is a leading provider of end-to-end software solutions and IT consulting services. We are headquartered in Fremont, California, with clients across the Silicon Valley and other major technology hubs.
Job SummaryWe are seeking a highly skilled Design Verification Engineer to join our team. The successful candidate will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
Key Responsibilities- Develop test plans and coverage metrics from specifications and write block and chip-level tests.
- Create PERL/Python scripts to automate creating verification environments, test generation, and debugging.
- Analyze failures of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
- Design low-power test cases using UPF or CPF to verify the desired power intent of the SoC.
- Collaborate with architects to determine use-case scenarios to simulate.
- 7+ years of experience in pre-silicon design verification.
- Proficiency in C-shell scripting, Verilog-HDL & System Verilog.
- Strong knowledge in SV Assertions, UVM/OVM, and functional code coverage.
- SOC Verification experience using ARM Cortex Microcontroller is required.
- Experience with advanced peripheral bus Verification IP's such as GPIO, UART, SPI, SW, JTAG, and I2C.
- Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e. Spyglass) will be helpful.
- Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
- Exposure to FPGA programming and FPGA tools will be helpful.
- Independent, self-motivated with good analytical & communication skills.
All your information will be kept confidential according to EEO guidelines.