Senior Design Verification Engineer

4 weeks ago


Santa Clara, California, United States Astera Labs Full time

Astera Labs is a global leader in innovative connectivity solutions that unlock the full potential of AI and cloud infrastructure.

Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a scalable and customizable architecture.

Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering flexible and interoperable products.

Discover how we are transforming modern data-driven applications at Astera Labs.

We are seeking a Principal Design Verification Engineer with proven experience in working on industry-standard protocols such as PCIe/CXL/DDR/Ethernet.

Using your coding and protocol expertise, you will contribute to the functional verification of designs from creating block-level and system-level verification plans to writing test sequences, executing tests, collecting, and closing coverage.

Key Responsibilities:

  • Developing test plans and related test sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.
  • Creating user-controlled random constraints in transaction-based verification methodology.
  • Writing assertions, cover properties, and analyzing coverage data.
  • Using Verification IPs from 3rd party vendors for PCIe/CXL (with focus on Gen3 or above).
  • Developing VIP abstraction layers for sequences to simplify and scale verification deployments.

Requirements:

  • Strong academic and technical background in electrical engineering.
  • At least 10 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Knowledge of industry-standard simulators, revision control systems, and regression systems.
  • Authorized to work in the US and start immediately.

Preferred Experience:

  • Physical Layer, Link Layer, and Transaction Layer verification expertise in PCIe/CXL protocol.
  • Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports.
  • Experience in analyzing performance metrics of CXL/PCIe.
  • Experience in system-level verification for PCIe/CXL.

Compensation:

The base salary range is $160,000 - $240,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is an equal opportunity employer and welcomes applications from diverse candidates. We believe that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences.



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