Hardware Engineer for 2.5D and 3D Packaging Solutions

3 weeks ago


Sunnyvale, California, United States Google Full time

At Google, we're committed to pushing the boundaries of innovation and developing custom silicon solutions that power our direct-to-consumer products.

The US base salary range for this full-time position is $193,650-$288,900 + bonus + equity + benefits.

About the Role:

  1. We're seeking a highly skilled Hardware Engineer to join our team and contribute to the design and development of advanced packaging solutions.
  2. You'll work closely with cross-functional teams, including ASIC designers, package designers, and system architects, to ensure seamless integration and optimal performance.

Responsibilities:

  1. Develop and implement interposer routing strategies for 2.5D and 3D packaging, ensuring high-speed effects, signal integrity, and efficient power distribution.
  2. Collaborate with designers to create redistribution layer (RDL) designs and perform technical evaluations of interposers, advanced packaging, process nodes, and IP.
  3. Contribute to the creation of application-specific integrated circuit (ASIC) top-level I/O planning and RDL routing.
  4. Evaluate and provide recommendations on interposer layout, specification requirements, collaterals, and milestone timelines.
  5. Participate in design reviews, ensure compliance with industry standards, and maintain documentation of design decisions and results.

Requirements:

  1. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
  2. Minimum 10 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
  3. Expertise in routing through custom routing or PnR tool routing.
  4. Familiarity with layout, physical verification, Design for Manufacturability (DFM), power, and signal integrity analysis using industry-standard tools.
  5. Experience with Controlled-Collapse Chip Connection (C4) bumps, micro bumps, Deep Trench Capacitor (DTC), Through-silicon via (TSV), etc.

Preferred Qualifications:

  1. Experience leading one or more aspects of interposer or package design.
  2. Knowledge of techniques for testing and debugging interposer designs, including electrical and thermal considerations.
  3. Understanding of semiconductor device physics and transistor characteristics.
  4. Able to communicate complex technical ideas effectively to both technical and non-technical stakeholders.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, or Veteran status.



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