Senior ASIC Design Engineer

2 months ago


Santa Clara, California, United States Apple Full time
About the Role

We are seeking a highly skilled ASIC Design Engineer to join our team at Apple. As a key member of our SoC Design team, you will be responsible for designing and developing high-performance on-chip interconnects for our next-generation SOC's.

Key Responsibilities
  • Analyze architectural requirements and define scalable interconnect components
  • Design and implement high-quality RTL with embedded assertions and cover points
  • Collaborate with cross-functional teams to explore solutions for improving performance while minimizing power and area
  • Work closely with design verification and formal verification teams to debug and verify functionality and performance
Requirements
  • Extensive experience in front-end ASIC RTL digital logic design using Verilog or System Verilog
  • Tight-knit collaboration skills with excellent written and verbal communication skills
  • Familiarity with multiple power domains, multiple clock domains, and asynchronous interfaces
  • Strong understanding of flow control, arbitration, on-chip interconnects, QoS, topology, and performance analysis
  • Experience with implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, logic equivalence checks
Preferred Qualifications
  • Bachelors degree + 10 years of industry experience
  • Experience with ASIC IP development using extensive flow automation
About Apple

At Apple, we're committed to innovation and excellence. We're looking for talented individuals who share our passion for creating cutting-edge technology that makes a difference in people's lives. If you're a motivated and experienced ASIC Design Engineer looking for a new challenge, we encourage you to apply for this exciting opportunity.



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