Phy Verification Engineer/Lead

2 days ago

San Jose, California, United States InnoPhase IoT Full time
About InnoPhase IoT

We're a team of innovators passionate about creating cutting-edge wireless IoT solutions. Our mission is to revolutionize the industry with our expertise in ultra-low power (ULP) wireless technology. We're committed to fostering a culture of collaboration, creativity, and growth, where every voice is heard and every team member has the opportunity to make a meaningful impact.

Job Description

We're seeking a highly skilled Phy Verification Engineer/Lead to join our team. As a key member of our verification team, you'll be responsible for designing and developing high-quality UVM testbenches for wireless PHY and MAC layers. Your expertise in low-power WiFi and BT/BLE verification will be instrumental in ensuring the success of our IoT wireless solutions.

Key Responsibilities
  • Design and develop hierarchical UVM testbenches for wireless PHY and MAC layers
  • Collaborate with design and system engineers to develop constraint random testbenches with reference C models
  • Identify bottlenecks in design and verification coverage and provide feedback on potential optimizations
  • Work closely with verification and validation teams on test-plans, coverage-analysis
  • Maintain releases, run, and track regressions, and identify functional and code coverage gaps
  • Develop and refine design, verification, and analysis tools and flows, as needed
Requirements
  • BSEE or MSEE with experience in UVM testbench development, constraint random testing, and coverage analysis
  • 12+ years of experience in RTL and gate-level verification
  • Basic understanding of digital signal processing theory
  • Experience in verifying WiFi physical layer and/or other physical layers like cellular, Bluetooth, Zigbee, UWB, and/or Ethernet technologies
  • Ability to work independently and proactively identify and resolve issues
  • Experience with Incisive/Xcelium/VCS, Verdi, or equivalent tools
  • Enjoy debugging and problem-solving in a team environment
Preferred Qualifications
  • Experience in verifying low-power designs involving multiple power and voltage domains
  • Establish system verilog assertions for functional verification
  • Embedded SW and HW design is a strong plus
  • Experience with Python, Perl, Tcl, C/C++, and shell scripts
  • Experience with lab debug, multi-team, and multi-site working environment is a strong plus
  • Experience with ASIC and FPGA synthesis flows utilizing industry-leading flows
  • Experience using PowerArtist/Joules and providing actionable feedback into design

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