Principal ASIC Design Engineer

10 hours ago


Sunnyvale, California, United States Fortinet Full time
Job Title: Principal ASIC Design Engineer

Fortinet is seeking a highly skilled Principal ASIC Design Engineer to join our R&D team. This role involves designing cutting-edge high-performance ASICs from specification to RTL implementation.

Key Responsibilities:
  • Develop network processing ASIC/FPGA architecture and microarchitecture specification
  • Design high-performance and high-quality ASIC/FPGA design from specification to RTL implementation
  • Perform ASIC/FPGA verification, lint/cdc, synthesis, timing analysis, and IP integration
  • Implement network packet processing systems using Altera/Xilinx FPGA
  • Participate in system/board-level bring-up, debugging, and support
Requirements:
  • 8 years or more of networking or processor design experience
  • Strong track record of ASIC/FPGA design from concept to mass production
  • Hands-on experience in Verilog HDL coding and verification
  • Experience with Altera/Xilinx FPGA architecture, tools, and IP portfolio
  • Ethernet and TCP/IP networking concepts and protocols knowledge
  • Knowledge of System Verilog and UVM verification methodology
Benefits:
  • Competitive salary range: $160,000-$220,000
  • Medical, dental, vision, life, and disability insurance
  • 401(k) and comprehensive leave program
  • 11 paid holidays, vacation time, and sick time
About Us:

Fortinet secures the largest enterprise, service provider, and government organizations around the world. Our Security Fabric architecture delivers security without compromise to address the most critical security challenges. We empower our customers with intelligent, seamless protection across the expanding attack surface and the power to take on ever-increasing performance requirements of the borderless network.



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