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Senior ASIC Physical Design Engineer

2 months ago

Sunnyvale, California, United States SpaceX Full time
Job Title: Senior SOC/ASIC Physical Design Engineer

Join SpaceX as a Senior SOC/ASIC Physical Design Engineer and contribute to the development of cutting-edge silicon for deployment in space and ground infrastructures around the globe.

About the Role:

We are seeking a highly motivated and experienced Physical Design Engineer to join our team. As a Senior SOC/ASIC Physical Design Engineer, you will be responsible for developing and implementing physical design methodologies and automation scripts for various implementation steps. You will work closely with the ASIC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs.

Responsibilities:
  • Perform partition synthesis and physical implementation steps, including synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency, and other signoff checks.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs.
  • Resolve design/timing/congestion and flow issues, identify potential solutions, and drive execution.
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration, and voltage drop.
Requirements:
  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of ASIC and/or physical design flow development experience in industry.
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows.
  • Strong experience with industry-standard EDA tools, including understanding of their capabilities and underlying algorithms.
  • Knowledge of deep sub-micron FinFET and CMOS solid-state physics.
  • Knowledge of CMOS digital design principles, basic standard cells, their functionality, and standard cell libraries.
  • Understanding of CMOS power dissipation in deep submicron processes, leakage/dynamic.
  • Familiar with CMOS analog circuit and physical design.
  • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows.
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.).
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment.
Additional Requirements:
  • Must be willing to work extended hours and weekends as needed.
Compensation and Benefits:

Base salary: $170,000.00 - $230,000.00 per year. Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.

You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.

You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence, and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability, or any other legally protected status.