Senior Digital Verification Engineer

3 weeks ago


Redmond, Washington, United States Wipro Full time
Job Overview

We are seeking an experienced Senior Digital Verification Engineer to join our design verification team at Wipro. As a senior member of our team, you will be responsible for leading the development and implementation of testbenches for digital designs using SystemVerilog Universal Methodology (UVM) and Python.

Key Responsibilities:
  • Lead the development and implementation of testbenches for digital designs using UVM and Python
  • Mentor junior engineers in testbench development and debugging
  • Collaborate with designers to identify requirements and develop test plans
  • Implement unified power format (UPF) power aware simulation/emulation
  • Review and approve test plans and results

Requirements:

  • 10+ years of experience in digital verification
  • Strong leadership and mentoring skills
  • Excellent knowledge of UVM and Python
  • Good understanding of UPF and its applications
  • Experience with coverage collection and closure

Estimated Salary: $200,000 - $280,000 per annum



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