Verification and Validation Specialist

1 week ago


Redmond, Washington, United States Wipro Full time
About the Role

We are looking for an experienced Verification and Validation Specialist to join our design verification team at Wipro. In this role, you will be responsible for developing and implementing testbenches for digital designs using SystemVerilog Universal Methodology (UVM) and Python.

Key Responsibilities:
  • Design and implement testbenches for digital designs using UVM and Python
  • Collaborate with designers to identify requirements and develop test plans
  • Set up and debug continuous integration and regression testing for simulation at both RTL and gate level netlist
  • Implement unified power format (UPF) power aware simulation/emulation
  • Analyze and report on test results

Requirements:

  • 8-12 years of experience in digital verification
  • Strong knowledge of UVM and Python
  • Good understanding of UPF and its applications
  • Experience with coverage collection and closure
  • Excellent problem-solving and analytical skills

Estimated Salary: $150,000 - $220,000 per annum



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