Design Verification Specialist

2 days ago


Austin, Texas, United States Ursus Inc Full time
Job Title: Design Verification Engineer

Ursus Inc is seeking a highly skilled Design Verification Engineer to contribute to the functional verification of GPU Subsystems.

Responsibilities:
  • Triage regression failures and update testbenches
  • Debug functional errors in RTL models using simulation and debug tools
  • Maintain efficient and clean regression status
  • Develop scalable SystemVerilog/UVM testbenches for unit level and/or cluster level verification
  • Review architecture and micro-architecture specifications
  • Closely work with architects and RTL designers
  • Define, maintain, and execute unit level and/or cluster level verification test plans
  • Generate and run test cases on logic simulation models
  • Code functional coverage models and SystemVerilog assertions
  • Drive functional coverage and code coverage to closure
  • Integrate C++ reference models into scoreboards
Requirements:
  • 5-15 years of industry experience in a design verification role
  • Proficient in SystemVerilog/UVM/OVM, OOP/C++
  • Knowledge of GPU, experience with shader, texture, or memory system a plus
  • Experience with code coverage and functional coverage driven verification methodology
  • Experience in creating, running, and debugging SystemVerilog/UVM constraint-random testbenches
  • Excellent working knowledge of scripting languages such as Python or Perl
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines
  • Strong functional verification experience including test planning, testbench architecture, test/coverage model/assertion development
  • Strong debugging skills
  • Strong programming skills with good understanding of algorithms and data structures
  • Good verbal and written communication skills


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