Design Verification Specialist

6 days ago


Austin, Texas, United States Bayone Full time
Job Title: Design Verification Engineer

Bayone is seeking a highly skilled Design Verification Engineer to join our System IP team. As a key member of our team, you will be responsible for contributing to the functional verification of System IP, including coherent interconnect, and executing test plans.

Key Responsibilities:
  • Develop and implement functional verification strategies for complex System IP designs.
  • Create feature-based test plans and execute them efficiently.
  • Work closely with the DV team and designers to build verification environments.
  • Develop UVM sequences, tests, scoreboards, monitors, and checkers.
  • Write SVA assertions and achieve functional and code coverage closure.
  • Perform regression triaging and debug.
  • Collaborate with the team to achieve multiple tasks and projects.
Requirements:
  • BS/MS/PhD (or equivalent experience) in a relevant field.
  • 12+ years of experience in verification, with a strong background in System Verilog and UVM.
  • Deep understanding of constrained randomization and efficient test suite development.
  • Proficient in script languages like Perl or Python, and working knowledge of C++.
  • Good knowledge of memory subsystems, including interconnect, last-level cache, and coherency.
  • Familiarity with Arm AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect and bus protocols.
  • Excellent communication skills and ability to work as a team player.


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