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Design Verification Engineer

2 months ago

Austin, Texas, United States Synapse Design Inc. Full time

We are seeking a highly skilled Design Verification Engineer to join our team at Synapse Design Inc. in San Jose, CA.

Job Summary:

The successful candidate will be responsible for designing and verifying complex digital and mixed-signal ICs using advanced EDA tools and methodologies.

Key Responsibilities:

  • Develop and execute verification plans for SOCs with embedded ARM CPUs, DSPs, and peripherals.
  • Design and implement HVL (UVM or System Verilog with OVM) testbenches and C/C++/Perl/TCL scripts for verification.
  • Collaborate with cross-functional teams to integrate verification results into the design flow.
  • Stay up-to-date with industry trends and emerging technologies in digital and mixed-signal IC design and verification.
  • Participate in code reviews and contribute to the development of best practices for verification methodologies.

Requirements:

  • Strong background in digital and mixed-signal IC design and verification.
  • Proficiency in HVL (UVM or System Verilog with OVM), C/C++, Perl, TCL, and EDA tools.
  • Experience with signal processing and MATLAB/Simulink flows is a plus.
  • Familiarity with assertion writing and formal verification is a plus.
  • Excellent communication and teamwork skills.

What We Offer:

Competitive salary and benefits package, opportunities for professional growth and development, and a dynamic work environment.