Senior SOC Physical Design Engineer
1 week ago
Synopsys, Inc. is a leader in chip design, verification, and IP integration. We empower the creation of high-performance silicon chips and software content.
As a Senior SOC Physical Design Engineer, you will be responsible for implementing SOC physical design from RTL to GDSII. You will work on top-level and block-level physical design implementation and design closure, developing and improving methodologies and flows within Synopsys and customer environments.
This role requires collaboration with cross-functional teams, acting as an extension of the customer's design team. Your expertise in managing complex IP sub-systems, top-level floor-planning, bump-maps, RDL IO Pad/Ring creation/verification, and power grid creation/verification will be invaluable.
We are seeking a seasoned professional with 8+ years of experience in SOC physical design. Proficiency with Synopsys tools such as DC, DCG, DC TOPO, Fusion Compiler/ICC2, and Lynx is essential. Experience with GlobalFoundries, TSMC, and Samsung technology nodes is also required.
The ideal candidate will be a proactive problem solver with a keen eye for detail, able to manage risks and contingency plans effectively. They should be passionate about innovation and continuous improvement, with the ability to work independently and drive projects to successful completion.
This position offers a comprehensive salary range, estimated to be around $180,000-$220,000 per year, depending on experience. In addition, we offer a range of health, wellness, and financial benefits to cater to your needs.
In this role, you will contribute to the successful implementation and design closure of SOC projects, enhancing Synopsys' reputation for delivering high-quality silicon solutions. You will drive innovation in SOC physical design methodologies and flows, ensuring first-time right silicon through meticulous design and verification processes.
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