Senior DDR IP Design Engineer

2 weeks ago

Sunnyvale, California, United States SpaceX Full time
Job Title: Senior DDR IP Design Engineer

At SpaceX, we're pushing the boundaries of innovation and technology. As a Senior DDR IP Design Engineer, you'll play a critical role in developing cutting-edge memory controller IP for our next-generation SoCs. Your expertise will help us deliver high-performance, low-power solutions that enable connectivity in places it has previously not been available, affordable, or reliable.

Responsibilities:
  • Own the high-quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects and addressing issues.
  • Responsible for Memory Controller/PHY IP core development and integration.
  • Responsible for RTL design, synthesis, timing constraints, power estimation, and timing analysis using industry-leading CAD tools in the latest generation process technologies.
  • Collaborate with chip architects, software engineers, and other subsystem owners to develop high-performance Memory controller/PHY solutions.
  • Write detailed design specifications and test plans in close collaboration with architecture, package, and verification engineers.
  • Support silicon bring-up, performance, and power characterization for memory subsystems.
  • Drive functional verification including test plan reviews, and functional and code coverage as well as timing closure for your designs.
Requirements:
  • BS in Electrical Engineering, Computer Engineering, or Computer Science.
  • 8+ years of experience working with ASICs and the VLSI design flow.
  • Experience in RTL development and verification using Verilog and/or SystemVerilog.
Preferred Skills and Experience:
  • MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Knowledge of DDR/LPDDR DRAM protocols and experience analyzing/debugging DDR interfaces and protocols.
  • Experience in the development of Memory Controller and PHY IPs.
  • Experience working with Memory IP, Error checking Code (ECC), and building scalable, efficient flows and processes.
  • Experience with designing state machines, data paths, arbitration, and clock domain crossing (CDC) logic.
  • Exposure to Design For Test (DFT), understanding of scan, and writing DFT-friendly RTL.
  • Experience developing or integrating IPs with AMBA AXI, ACE-Lite, and CHI interfaces.
  • Familiarity with Unified Power Format (UPF) for simulation and synthesis.
  • Programming skills in C, PERL/Python.
Additional Requirements:
  • Ability to work long hours and weekends as necessary to support critical milestones.

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