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Senior ASIC Digital Design Engineer

2 months ago

Sunnyvale, California, United States Synopsys, Inc. Full time
About Synopsys, Inc.

Synopsys, Inc. is a leading provider of silicon IP solutions, offering a broad portfolio of predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. Our mission is to empower customers to integrate more capabilities into their SoCs, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk.

Job Summary

We are seeking a highly skilled Senior ASIC Digital Design Engineer to join our Solution Group, DDRPHY IP team. As a key member of our team, you will be responsible for innovating and developing world-class market-leading DesignWare DDRPHY IP solutions.

Key Responsibilities
  • Digital Microarchitecture Definition and Documentation
  • RTL Logic Design, Debug, and Verification for Best Timing, Area, and Power
Requirements
  • BS/MS in Electronics Engineering with at least 5 years of design experience
  • Experience with synthesizable Verilog and System Verilog design concepts and implementation
  • Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
  • Exhibit excellent communication skills and be self-motivated
  • Understanding of DDR memory and DDRPHY architecture is a plus
Compensation and Benefits

The base salary range for this role is between $122,000-$182,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.

Equal Employment Opportunity

Synopsys, Inc. is an equal employment opportunity employer and considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.