Senior Principal DFT Architect

7 hours ago

San Jose, California, United States ARM Full time
Job Overview:

Arm's Solutions group DFT team is responsible for implementing Design for Test (DFT) solutions for System-on-Chip (SOC) designs across various industries, including client, datacenter, automotive, and IoT. We collaborate closely with internal teams, including RTL, Verification, Physical Implementation, and Test engineering, to ensure seamless project execution from investigation to tape-out and silicon test/characterization.

Responsibilities:
  • Design and implement DFT solutions for SOC designs, catering to multiple industries and business lines.
  • Coordinate DFT requirements across SOC, IP, and product teams to ensure efficient design and testing.
  • Develop and validate innovative DFT techniques for SOC and subsystems, leveraging industry-standard simulation tools.
  • Insert DFT logic into SOC and subsystems, and validate all DFT features using simulation tools.
  • Collaborate with multi-functional teams to support DFT RTL level insertion, synthesis, scan insertion, place-and-route, and static-timing-analysis and timing closure.
  • Participate in ATE-targeted test patterns, validation, and silicon debug.
  • Work closely with Test and product engineering teams on silicon characterization and validation.
Requirements:
  • Senior Principal DFT Architect with 16+ years of experience in Design for Test.
  • 10+ years of experience in handling DFT architecture for complex SOCs in leading technology nodes.
  • Core DFT skills include Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, DFT mode timing constraints, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
  • Experience with 2.5D and 3D test.
  • Experience coding Verilog RTL, TCL, and/or Perl.
Nice to Have:
  • Familiarity with SOC style architectures, including multi-clock domain and low power design practices.
  • Previous experience managing a team of DFT Engineers.
  • Familiarity with Arm IP, including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug.
  • Background in design, implementation, and timing convergence.
  • Experience leading datacenter SOCs.
  • Experience with Cadence and/or Synopsys DFT and simulation tools.

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