Senior Principal DFT Architect

1 week ago


San Jose, California, United States ARM Full time
Job Overview

Arm's Solutions group DFT team is responsible for implementing DFT for SOC across various lines of business, including client, datacenter, automotive, and IOT. We collaborate closely with Arm's partners and internal teams to deliver innovative DFT solutions throughout the project lifecycle.

Responsibilities
  • Design and implement DFT solutions for SOC catering to multiple lines of business.
  • Coordinate DFT requirements across SOC, IP, and product teams.
  • Develop and validate innovative DFT techniques on SOCs and sub-systems.
  • Insert DFT logic into SoC and sub-system level and validate all DFT features using industry-standard simulation tools.
  • Collaborate with multi-functional teams to support DFT RTL level insertion, synthesis, and scan insertion, place-and-route, and static-timing-analysis and timing closure.
  • Participate in ATE targeted test patterns, validation, and silicon-debug.
  • Work closely with Test and product engineering teams on silicon characterization and validation.
Requirements
  • Senior Principal DFT Architect with 16+ years of proven experience in Design for Test.
  • 10+ years of experience handling DFT architecture for complex SOCs in leading technology nodes.
  • Core DFT skills include Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, DFT mode timing constraints, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
  • Experience with 2.5D and 3D test.
  • Experience coding Verilog RTL, TCL, and/or Perl.
Nice to Have
  • Familiarity with SoC style architectures, including multi-clock domain and low power design practices.
  • Previous experience managing a team of DFT Engineers.
  • Familiarity with Arm IP, including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug.
  • Background in design, implementation, and timing convergence.
  • Experience leading datacenter SOCs.
  • Experience with Cadence and/or Synopsys DFT and simulation tools.
Compensation

Salary range: $283,305 - $383,295. We value people as individuals and offer a competitive and equitable total reward package.



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