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DFT Architect Lead

2 months ago

San Jose, California, United States ZipRecruiter Full time
Job Description

**Job Overview:**

As a key member of the Arms Solutions group DFT team, you will be responsible for implementing Design for Test (DFT) solutions for System-on-Chip (SOC) designs catering to multiple business lines, including client, datacenter, automotive, and IoT. You will collaborate closely with internal RTL, Verification, Physical Implementation, and Test engineering teams to ensure seamless integration and delivery of DFT solutions.

**Responsibilities:**

  • Architect DFT solutions for SOC designs, ensuring optimal testability and reliability.
  • Coordinate DFT requirements across SOC, IP, and product teams to ensure alignment and effective implementation.
  • Implement and validate innovative DFT techniques on SOCs and sub-systems, leveraging industry-standard simulation tools.
  • Insert DFT logic into SoC and sub-system levels, and validate all DFT features using industry-standard simulation tools.
  • Work closely with multi-functional teams to support DFT RTL level insertion, synthesis, and scan insertion, place-and-route, and static-timing-analysis and timing closure.
  • Participate in ATE targeted test patterns, validation, and silicon-debug.
  • Collaborate with Test and product engineering teams on silicon characterization and validation.

**Requirements and Qualifications:**

  • 16+ years of proven experience in Design for Test (DFT) with a strong background in SOC design and test.
  • 10+ years of experience handling DFT architecture for complex SOCs in leading technology nodes.
  • Core DFT skills considered crucial for this position include:
    • Siemens DFT tools
    • Streaming Scan Network (SSN)
    • Scan compression and insertion
    • Memory BIST and repair scheme implementation
    • Logic BIST
    • JTAG/IJTAG
    • At-speed test
    • ATPG
    • Fault simulation
    • DFT mode timing constraints
    • Back-annotated gate level verification
    • Silicon debug
    • Memory and scan diagnostics
  • Experience with 2.5D and 3D test
  • Experience coding Verilog RTL, TCL, and/or Perl

**Nice to Have Skills and Experience:**

  • Familiarity with SOC style architectures, including multi-clock domain and low power design practices.
  • Previous experience managing a team of DFT Engineers.
  • Familiarity with Arm IP, including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug.
  • Background in design, implementation, and timing convergence.
  • Experience in leading datacenter SOCs.
  • Experience with Cadence and/or Synopsys DFT and simulation tools.