Senior Design Engineer
5 days ago
Cadence Design Systems is seeking a highly skilled Senior Design Engineer to join our team as a Principal Design Engineer - Mixed-Signal Solutions. As a key member of our engineering team, you will be responsible for defining and implementing mixed-signal solutions, verification plans, models, and roadmaps to deliver complete Mixed-Signal DV and emulation solutions.
Key Responsibilities- Architect, develop, champion, and implement metric-driven mixed-signal verification solutions in areas such as digital, DMS, AMS, and emulation testbench creation and generation.
- Automatic model generation and testing.
- Cadence Design Systems AMS simulation flows.
- Mixed-Signal Assertions and Checkers.
- Synthesizable and Non-Synthesizable Behavioral Modeling and Model Validation Methodologies.
- Mixed-Signal VIP integration and testing.
- Mixed-Signal emulation flows and practices.
- Power intent verification including Low power states, state retention, and CPF/UPF integration.
- PUSH technology for mixed-signal modeling, simulation, and DV to improve mixed-signal verification efficiency and accuracy.
- Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters, and custom solutions.
- Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification from conception through simulation and emulation.
- Develop efficient debug solutions and techniques.
- Develop an efficient and accurate full-stack mixed-signal methodology for the entire IP stack from the controller to the analog circuit.
- Propagate mixed-signal knowledge and mentor junior engineers.
- Collaborate closely with digital, analog, firmware, test, and customer engineers, internal methodology and tool development teams, and customer management and engineering support teams.
- Years of experience in working with digital and analog mixed-signal environments and teams.
- Good written and verbal cross-functional communication skills.
- Proven experience in most of the following: creating verification infrastructure, scripting of verification flows, design automation, debugging verification test cases, knowledge of existing and upcoming standards, and knowledge of multiple programming languages.
- Knowledge of Cadence Design Systems tools and mixed-signal methodology is a plus.
- Knowledge of Palladium/Protium or other hardware accelerator tools is a plus.
- Knowledge of System Verilog and UVM Test environment and methods is a plus.
- Working knowledge of revision control tools is a plus.
- Education Level: Bachelor's Degree (MSEE Preferred).
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