High Performance ASIC Design Engineer
6 days ago
We are seeking an experienced ASIC Design Engineer to join our team in Cupertino, California. As a key member of our Hardware Technologies group, you will play a critical role in designing our next-generation, high-performance, power-efficient system-on-chips (SoCs).
Your primary responsibility will be to ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.
In this highly visible role, you will be at the center of the Pixel IP design effort to capture and display beautiful images and video. You will collaborate with all disciplines, making a critical impact getting functional products to millions of customers quickly.
About the Role
- You will work closely with many cross-functional teams (chip integration, physical design, power, logic design, and verification) to build high performance and low power pixel processing engines.
- Your expertise in integrating large systems-on-a-chip, low-power design techniques, and front-end implementation will enable the team to deliver high performance and low power pixel processing engines on time.
- Your tasks will include integrating large pixel-processing subsystems using SystemVerilog, connecting to high-performance on-chip networks using virtual memory addressing, adding Design-For-Test (DFT) logic, and managing clocks, resets, and power domains.
- You will write detailed micro-architectural specifications.
- You will perform front-end implementation, including logic synthesis, clock & reset domain-crossing checks, static timing analysis, power analysis, logic equivalence checking.
- You will work with Physical Design teams for physical floorplanning and timing closure.
- You will collaborate with cross-functional teams to explore solutions that maximize performance while minimizing power and area.
- You will work closely with design verification and formal verification teams to debug and verify functionality and performance.
Requirements
- BS degree in Computer Science or related field.
- Minimum 0 years relevant industry experience.
- Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog.
- Industry exposure to and knowledge of ASIC/FPGA design methodology, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.
- Experience with system design methodologies that contain multiple clock domains.
- Experience in low-power design issues, tools, and methodologies including UPF power intent specification highly desired.
- Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
- Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).
- Good collaboration skills with strong written and verbal communication skills.
- Experience working cross-functionally with integration, design, and verification teams to specify, design, and debug digital systems.
Compensation and Benefits
The estimated salary for this role is between $121,900 and $183,600 based on your location and level of experience. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Apple is an Equal Opportunity Employer
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