Senior Design Verification Engineer
3 weeks ago
Arteris IP is seeking a highly skilled Senior Design Verification Engineer to join our team. As a key member of our verification team, you will be responsible for designing and delivering interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs.
Key Responsibilities:
- Develop and execute RTL verification test/coverage at system level
- Perform performance verification and power-aware verification
- Triage regressions and debug RTL designs in Verilog and System Verilog
- Improve and refine verification process, methodology, and metrics
- Integrate vendor provided VIPs for unit and system level verification
Requirements:
- 10 or more years of design and verification experience
- Strong RTL (Verilog) and UVM/C test bench debugging skills
- Experience integrating vendor provided VIPs for unit and system level verification
- Experience with Arm AMBA protocols
About Arteris IP: Arteris IP is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today's electronic systems. Our network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so our customers can focus on dreaming up what comes next.
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