Verification Engineer

3 weeks ago


Austin, Texas, United States Correct Designs Full time

We are seeking a talented Verification Engineer to join our team at Correct Designs. As a Verification Engineer, you will be responsible for verifying complex design blocks using SystemVerilog and UVM verification environments.

Key Responsibilities:

  • Verify complex design blocks using SystemVerilog and UVM verification environments
  • Develop and execute pre-silicon verification test plans
  • Develop directed and random verification tests to validate block and IP functionality
  • Develop verification components and tools
  • Develop verification functional coverage using industry standard coverage analysis tools/methods
  • Debug regression fails
  • Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

Requirements:

  • 3 or more years of proven verification experience in a hardware development setting
  • Strong background in SystemVerilog and UVM verification methodologies
  • Strong debug skills and experience with debug tools such as DVE/Verdi
  • Proficiency in Object Oriented programming, computer architecture and data structures
  • Strong analytical/problem solving skills and pronounced attention to details
  • Strong interpersonal and communication skills
  • Must be comfortable working across geographies

Preferred Skills:

  • Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
  • Experience in other related domains such as formal verification, RTL design, or software development

Education:

Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science



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