Senior Synthesis Engineer
3 weeks ago
Mega Cloud Lab is seeking a highly skilled Senior Synthesis Engineer to join our team in Santa Clara, CA. As a key member of our design team, you will be responsible for developing and implementing synthesis constraints at module and full chip levels.
Key Responsibilities- Design and implement synthesis constraints at module and full chip levels
- Promote subsystem-level RDC/CDC constraints to SoC top level
- Debug and triage Lint CDC/RDC errors or issues
- Convert spyglass constraints to realintent constraints
- Create lint RDC/CDC constraints at IP level, full chip, or top level
To be successful in this role, you will need:
- 8-10 years of experience in designing synthesis constraints at module and full chip levels
- Experience in promoting subsystem-level RDC/CDC constraints to SoC top level
- Ability to debug and triage Lint CDC/RDC errors or issues
- Knowledge of converting spyglass constraints to realintent constraints
- Ability to create lint RDC/CDC constraints at IP level, full chip, or top level
We offer a competitive salary range of $175,000 - $225,000 per year, depending on experience. Additional benefits include medical, dental, and vision insurance, 401(k) matching, and paid time off.
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