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Senior ASIC Physical Design Expert

2 weeks ago


Santa Clara, California, United States Efficient Computer Full time
About the Role

Efficient Computer is seeking a highly skilled Senior ASIC Physical Design Engineer to join our team. As a key member of our design team, you will be responsible for delivering high-quality physical designs for our cutting-edge products.

Job Summary
  • Design and deliver high-performance ASICs in advanced technology nodes
  • Develop and implement low-power techniques and design-technology co-optimization strategies
  • Collaborate with cross-functional teams to integrate digital and analog designs
  • Lead the physical design process from RTL to GDSII, ensuring timely delivery and quality standards
Key Responsibilities
  1. Take ownership of the physical design of multi-hierarchy low-power designs in advanced technology nodes
  2. Analyze, debug and fix placement-, cts-, routing-, and buffering- related design and flow issues
  3. Own and deliver designs meeting sign-off timing targets (setup/hold across multiple corners with OCV derating) within specified power envelope while managing constraints (sdc)
  4. Engage with the digital design team to understand the architecture to address congestion and timing issues through design modifications and functional Engineering Change Orders (ECOs)
  5. Engage with the DFT team to plan and provide early feedback on design decisions that relate to physical implementation
Required Qualifications
  • Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
  • Proven track record of delivering block (or SoC) RTL2GDSII for multiple tape-outs in 22nm or below process technologies
  • Experience with EDA flow using Cadence/Synopsys/Mentor tools for front-end (Synthesis/LEC), back-end (Place and Route), and verification/simulation (Physical Verification) with hierarchical design and abstraction techniques
  • Hands-on experience in place & route, power and clock-tree implementation, and timing convergence of high-frequency designs
  • Knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions
  • Experience with low power implementation typical in industry, including advanced knowledge of UPF standard (IEEE-1801)