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Digital Verification Engineer
1 month ago
We are seeking a skilled Digital Verification Engineer to join our team at Northrop Grumman. As a Digital Verification Engineer, you will be responsible for designing and developing digital verification solutions for our cutting-edge projects.
Key Responsibilities:- Design and develop digital verification solutions using HDL (VHDL/Verilog) and HVL (SystemVerilog)
- Develop and implement SystemVerilog Assertions (SVA) and Universal Verification Methodology (UVM)
- Collaborate with cross-functional teams to integrate verification solutions into our development process
- Develop and maintain documentation for verification solutions and processes
- Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred)
- 5 years of relevant experience (3 years with technical MS; 0 years with PhD)
- Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog)
- Experience with SystemVerilog Assertions (SVA)
- Knowledge of Universal Verification Methodology (UVM)
- Experience with scripting languages (Bash, Perl, Python, Tcl)
- Familiarity with Linux OS
- Familiarity with a coverage driven verification methodology from planning through closure
- Knowledge of industry standard interfaces
- Experience with object-oriented programming languages and concepts
- Advanced Degree either MS or PhD
- Active Full Top Secret/SCI security clearance with Polygraph
- Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience
- Competitive salary range: $109,900 - $164,900
- Discretionary bonus
- Long Term Incentives
- Health insurance coverage
- Life and disability insurance
- Savings plan
- Company paid holidays and paid time off (PTO)
Northrop Grumman is an Equal Opportunity/Affirmative Action Employer and is committed to hiring and retaining a diverse workforce. We are proud to be a leader in the aerospace and defense industry and are looking for talented individuals to join our team.