Senior FPGA Design Engineer
4 weeks ago
We are seeking a highly skilled Senior FPGA Engineer to join our team at Parallel Partners. As a Senior FPGA Engineer, you will be responsible for designing and developing high-performance FPGA-based systems.
Responsibilities:- Design and develop FPGA-based systems, including digital communication systems and DSP blocks.
- Develop high-level design requirements and block-level microarchitectures, and create specification documents.
- Optimize designs for area, speed, and power to meet system requirements, and analyze architectural tradeoffs.
- Develop test benches and test cases for block-level functional verification, emphasizing bitmatching and self-checking.
- Verify DSP blocks against fixed-point MATLAB models, and work in collaboration with systems engineers.
- Participate in SoC and FPGA integration activities, and prototype designs on FPGA.
- Perform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checks.
- Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs.
- Bring up and validate ASICs and FPGAs in the lab, utilizing various lab equipment.
- Collaborate with software engineers in developing production software for your designs.
- 8+ years of experience designing/testing with FPGAs (Xilinx, Altera, etc.).
- 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design.
- 3+ years of experience leading a team of Engineers.
- Expertise in any industry-standard testing frameworks (UVM, UVVM, OSVM, etc.).
- Experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C++, Tcl, Makefiles, Bash.
- Ability to guide Engineers with diverse skill sets towards deliverable goals.
- Some experience in designing DSP or digital communication system datapath blocks (e.g., filters, transforms, PHY blocks, loops, FEC, etc.).
- Experience in Xilinx advanced FPGAs, eval boards, and knowledge of FPGA design flow.
- Knowledge of different digital modulation techniques (e.g., PSK, QAM, OFDMA, etc.).
- Knowledge of wireless communications systems and standards (e.g., LTE, Wi-Fi, Bluetooth, etc.).
- Knowledge of industry-standard interfaces, protocols, and architectures: PCIe, Ethernet, AMBA, DDR, etc.
- Experience in developing automated, self-checking test benches.
- Knowledge or understanding of UVM verification framework.
- Experience in EDA tools such as simulators (e.g., Questa), lint checkers (e.g., Spyglass) synthesis (e.g., Synopsys Synplify), FPGA tools (e.g., Vivado).
- Experience in synthesis and static timing analysis, knowledge of timing closure techniques for high-speed designs.
- Experience in ASIC/FPGA/SoC system-level/toplevel integration.
- Familiarity with design for testability (DFT) and high-reliability ASIC design and implementations.
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