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Senior ASIC Design Engineer

2 months ago


Santa Clara, California, United States Apple Full time
About the Role

We are seeking a highly skilled ASIC Design Engineer to join our team at Apple. As a key member of our memory systems team, you will be responsible for designing and developing high-performance cache architectures that meet the demanding requirements of our mobile processing systems.

Key Responsibilities
  • Participate in the development of cache microarchitectures from specifications and model analysis
  • Explore architecture trade-offs in system performance, area, and power consumption with the performance analysis team
  • Develop and debug RTL designs of different sections of the cache
  • Work with the physical design team to close timing of the cache
Requirements
  • Development of memory systems
  • Experience in RTL/micro-architecture definition
  • Experience in PPA (performance/power/area) analysis
  • Knowledge of coherent memory systems or interconnect architectures
  • Strong cache design background, including good understanding of different memory organizations and trade-offs
  • Knowledge of memory subsystems and dram controllers
  • Hands-on experience with multi-processor cache coherence protocols
Education and Experience

Bachelor's Degree + 10 years of experience

What We Offer

At Apple, we offer a comprehensive compensation package, including base pay, discretionary bonuses, and commission payments. Our employees also have the opportunity to become Apple shareholders through our discretionary employee stock programs. Additionally, we offer a range of benefits, including comprehensive medical and dental coverage, retirement benefits, and reimbursement for certain educational expenses.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.