ASIC Design for Test Engineer
6 days ago
Cisco is seeking a highly skilled ASIC Design for Test Engineer to join our Silicon One development organization in San Jose, CA. As a key member of our team, you will be responsible for implementing Hardware Design-for-Test (DFT) features that support Automated Test Equipment (ATE), in-system test, debug, and diagnostics needs of our designs.
Key Responsibilities- Implement DFT Features: Develop and integrate DFT features into our designs to ensure testability and debuggability.
- Collaborate with Cross-Functional Teams: Work closely with Front-end RTL teams, backend physical design teams, and other stakeholders to drive DFT requirements early in the design cycle.
- Drive Quality Process: Lead the development of innovative DFT IP and play a key role in full chip design integration with testability features coordinated in the RTL.
- Post-Silicon Validation: Participate in the creation of innovative hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die, driving reusable test and debug strategies.
- Education: Bachelor's or Master's Degree in Electrical or Computer Engineering.
- Experience: 4+ years of related work experience with a broad mix of technologies, including Jtag protocols, Scan and BIST architectures, ATPG, and EDA tools like TestMax, Tetramax, and Tessent.
- Skills: Strong verbal skills, ability to thrive in a multifaceted environment, and scripting skills in Tcl, Python, or Perl.
- Verilog Design Experience: Developing custom DFT logic and IP integration, familiarity with functional verification.
- DFT CAD Development: Test architecture, methodology, and infrastructure.
- Test Static Timing Analysis: Post-silicon validation using DFT patterns.
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Senior ASIC Design for Test Engineer
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ASIC Design for Test Engineer
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San Jose, California, United States Cisco Full timeAbout the RoleCisco is seeking a highly skilled ASIC Design for Test Engineer to join our Silicon One development organization in San Jose, CA. As a key member of our team, you will be responsible for implementing Hardware Design-for-Test (DFT) features that support Automated Test Equipment (ATE), in-system test, debug, and diagnostics needs of our...
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