Senior ASIC Design for Test Engineer

4 days ago


San Jose, California, United States Cisco Systems, Inc. Full time
About the Role

Cisco Systems, Inc. is seeking a highly skilled Senior ASIC Design for Test Engineer to join our Silicon One development organization in San Jose, CA. As a Technical Lead for ASIC Implementation, you will be responsible for designing and developing comprehensive Design-for-Test (DFT) architectures that support ATE screening, in-system test, debug, and diagnostics needs of the design.

Key Responsibilities
  • Test Planning and Development: Responsible for thorough test planning and development of test benches to verify comprehensive DFT architecture.
  • Collaboration with Design Teams: Work closely with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
  • Post-Silicon Validation: Work with the team on post-silicon validation using DFT patterns and lead junior engineers to deliver expected implementations on schedule.
  • Innovative DFT & Test Strategy: Work with the team on innovative hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
Requirements
  • Experience: 7+ years of related work experience with a broad mix of technologies.
  • Education: Bachelor's or a Master's Degree in Electrical or Computer Engineering required.
  • Skills: Knowledge of the latest innovative trends in DFT, test, and silicon engineering; experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
What We Offer

Cisco Systems, Inc. offers a competitive salary and benefits package, as well as opportunities for professional growth and development. We are an equal opportunities employer and welcome applications from diverse candidates.



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