Highly Skilled ASIC Physical Design Engineer
2 weeks ago
We are seeking a highly skilled ASIC Physical Design Engineer to join our team at IBA InfoTech. The ideal candidate will have extensive experience in handling block and chip level implementation from netlist to GDSII, with a strong focus on timing closure and physical verification closure.
The successful candidate will have hands-on experience in handling blocks of sizes 1M instances and above at frequencies higher than 1GHz, as well as experience in handling lower tech nodes such as 3nm, 5nm, 7nm, 10nm, 16nm, etc.
The ideal candidate will also have excellent scripting skills in TCL, Perl, or Python, and experience in Synthesis and Formal is a plus. Additionally, the candidate should have excellent verbal and written communication skills, as well as the ability to work independently and as part of a team.
The successful candidate will be responsible for chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration, and ECO generation. They will also be responsible for handling blocks of high instance counts and complex designs, as well as experience with low power implementation and signoff, power gating, multiple voltage rails, and UPF knowledge.
The ideal candidate will have a strong understanding of signoff closure, including timing with SI and OCV, power, IR, and physical verification at both block and chip level. They will also have experience in block-level and full-chip integration, as well as knowledge of Synopsys or Cadence EDA Tool Suite, STA, PrimeTime-Si, PNR, and Python/TCL.
We offer a competitive salary and benefits package, as well as opportunities for professional growth and development. If you are a highly skilled ASIC Physical Design Engineer looking for a new challenge, please submit your application.
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Senior ASIC Physical Design Engineer
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