Senior Design Verification Engineer

23 hours ago


Austin, Texas, United States NextDeavor Full time
About the Role

We are seeking a highly skilled Design Verification Engineer to join our team at NextDeavor. As a key player in our expert team, you will be responsible for designing and delivering interconnect and memory hierarchy solutions for advanced mobile, telecom, automotive, and consumer SoC designs.

Key Responsibilities
  • Develop and debug advanced UVM-based test benches.
  • Define, document, develop, and execute RTL verification tests and coverage at the system level.
  • Conduct performance and power-aware verification.
  • Triage regressions and debug RTL designs using Verilog and SystemVerilog.
  • Improve and refine verification processes, methodologies, and metrics.
  • Apply UVM expertise to complex SoC projects, from test bench development to verification closure.
Requirements
  • Bachelor's of Science degree in EE, CS, or equivalent experience, MS Degree preferred.
  • 10+ years of design and verification experience, with a preference for interconnect verification experience.
  • Expertise in enhancing verification flows using scripting languages such as Shell scripts, Python, and JavaScript.
  • Strong skills in debugging RTL (Verilog) and UVM/C test benches.
  • Experience integrating vendor-provided VIPs for unit and system-level verification.
  • Familiarity with Arm AMBA protocols.
  • Experience with high-performance, low-power designs on highly visible projects.
What We Offer

We offer a competitive salary range of $150,000 - $200,000 annually, as well as a comprehensive benefits package, including medical, dental, and vision insurance, life insurance, disability insurance, and 401k matching.



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