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Senior/Staff Design Verification Engineer

2 months ago

Austin, Texas, United States NextDeavor Full time
About the Role

We are seeking a highly skilled Design Verification Engineer to join our team at NextDeavor. As a key member of our expert team, you will play a crucial role in designing and delivering interconnect and memory hierarchy solutions for advanced mobile, telecom, automotive, and consumer SoC designs.

Key Responsibilities
  • Develop and Debug Advanced UVM-Based Test Benches
  • Define, Document, Develop, and Execute RTL Verification Tests and Coverage at the System Level
  • Conduct Performance and Power-Aware Verification
  • Triage Regressions and Debug RTL Designs Using Verilog and SystemVerilog
  • Improve and Refine Verification Processes, Methodologies, and Metrics
  • Apply UVM Expertise to Complex SoC Projects, from Test Bench Development to Verification Closure
Requirements
  • Bachelor's of Science Degree in EE, CS, or Equivalent Experience, MS Degree Preferred
  • 10+ Years of Design and Verification Experience, with a Preference for Interconnect Verification Experience
  • Expertise in Enhancing Verification Flows Using Scripting Languages Such as Shell Scripts, Python, and JavaScript
  • Strong Skills in Debugging RTL (Verilog) and UVM/C Test Benches
  • Experience Integrating Vendor-Provided VIPs for Unit and System-Level Verification
  • Familiarity with Arm AMBA Protocols
  • Experience with High-Performance, Low-Power Designs on Highly Visible Projects
What We Offer

We offer a competitive salary range of $150,000 - $200,000 annually, as well as a comprehensive benefits package.