ASIC Front-end Implementation Engineer, Staff

2 weeks ago

Sunnyvale, United States Synopsys Full time

ASIC Front-end Implementation Engineer

Job Description and Requirements At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. We are looking for ASIC Front-end Implementation Engineers to join Synopsys Ethernet IP solutions Group based out of Bangalore which is developing Ethernet QoS/1G/10G/25G/100G/200G/400G/800G MAC controllers. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, RDC analysis, timing constraints, synthesis to build efficient IPs. Responsibilities:

Perform RTL Lint and work with the RTL Design Engineers to create waivers. Perform Clock Domain Crossing (CDC) and work with the RTL Design Engineers to analyse the complex clock domain crossings and sign off the CDC. Perform Reset Domain Crossing (RDC) Checks. Understand the Reset-Architecture by working with RTL Design Engineers and develop reset groups and the corresponding reset sequence for RDC. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Develop Timing Constraints for RTL-Synthesis and PrimeTime STA for IPs. Develop Power Intent Specification in UPF for the multi-Vdd designs. Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL and Physical Design Engineers to resolve them. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). Work closely with the RTL Design Engineers, DV Engineers, FPGA validation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. Key Qualifications and Experience:

Bachelor’s or Master’s degree

in electronics or electrical engineering or equivalent from reputed universities with 4-8 years of relevant experience in ASIC/SoC/IP Front-end Implementation. Experience with RTL design using Verilog or SystemVerilog. Knowledge of Clock Domain Crossing, Reset Domain Crossing, LEC. Experience with RTL Synthesis and design optimization for Power, Performance, Area. Be familiar with the Low power concepts & UPF/CPF format. Good understanding about Tech file, liberty, lef, def, gds & standard cells view generation process (Milkyway & NDM) and SRAM memories. Proficiency in Synopsys implementation tools (SpyGlass/VC-SpyGlass, Fusion Compiler/ Design Compiler, Prime Time, Formality, etc) or equivalent industry standard implementation tools is an advantage. Experience in managing multiple IP releases and collaborating with cross functional teams to support and debug timing, area, and power issues. Requires proficiency in scripting (TCL/Perl/Python) In addition, the candidate should have effective communication skills, should be a collaborator and possess good problem-solving skills. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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