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Senior Design Verification Engineer

2 months ago

Santa Clara, United States QuEST Global Full time

Senior Design Verification Engineer Experience Level: 7-20+ Years 4 Positions JOB DESCRIPTION 1- San Jose CA Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. Good knowledge of EDA tools. Experience with signal processing and MATLAB/Simulink flows a plus. Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus Familiarity with assertion writing and formal verification is a plus. JOB DESCRIPTION 2: Sunnyvale CA General DV skills, someone who can understand the specs, work with designers, write SV tests, and good at debug. Looking for mid-level experience JOB DESCRIPTION 3: Sunnyvale CA DV background, but more focused or specialized in the python scripting, tool implementation using python, looking for mid/sr level experience. JOB DESCRIPTION 3: Austin TX /Remote We need someone with good verification skills and preferably some experience with Arm IP and architecture. Some particular areas of experience would be: 1. ARM AMBA knowledge 2. System Verilog, system Verilog assertions 3. Nice to have: formal connectivity