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Senior Design Verification Engineer

1 month ago

Santa Clara, California, United States Astera Labs Full time
Astera Labs: Unlocking AI and Cloud Infrastructure Potential

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure.

Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable.

Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable.

Join Our Team of Verification Experts

We are seeking a skilled Senior Design Verification Engineer to contribute to the functional verification of our complex ASIC designs.

As a key member of our verification team, you will be responsible for the full life cycle of verification, from planning to writing tests to debugging, collecting and closing coverage.

You will work closely with our software and system validation teams to develop test plans and execute them in emulation platforms.

Key Responsibilities:
  • Develop and execute verification plans, including test planning, test sequence development, and debugging
  • Collaborate with RTL designers to debug failures and identify verification holes
  • Develop and maintain verification infrastructure using scripting tools (Perl/Python)
  • Work with verification IPs from 3rd party vendors with communication protocols such as PCI-Express, Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
Requirements:
  • Strong academic and technical background in electrical engineering
  • At least 5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications
  • Knowledge of industry-standard simulators, revision control systems, and regression systems
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision
Preferred Qualifications:
  • Experience with full verification lifecycle based on System Verilog/UVM/C/C++
  • Proven ability to mix and deploy hybrid techniques as in both directed and constrained random
  • Experience with different ways to bug and coverage hunting

Astera Labs is an equal opportunity employer and welcomes applications from diverse candidates. We offer a competitive salary range of USD 130,000 to USD 185,000, depending on location, experience, and pay of employees in similar positions.