Sr. Full Chip Physical Design Engineer

4 weeks ago


Irvine, United States SpaceX Full time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SR. FULL CHIP PHYSICAL DESIGN ENGINEER(SILICON ENGINEERING)As a member of our multifaceted ASIC team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.In this critical role, as a top level physical design engineer, you will be collaborating with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.RESPONSIBILITIES: Perform SOC top level physical design; floor-planning, I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, partition hardening, chip level clock, feedthrough, special interface, and interconnect planning, bus routing, sequential pipeline planning and top level design for testability (DFT) planningCollaborate with chip architects, ASIC engineers, package engineers and block level physical design engineers to drive, chip floorplan reviews and identify area, interconnect, IP integration, and floorplan improvement opportunitiesPerform chip timing budgeting and constraint pushdown to partition ownersWork with static timing analysis, physical verification, electromigration/voltage drop, noise and other signoff teams to achieve closure and tapeout on timeRun physical verification at chip level and provide feedback and guidance to block level physical design engineers to fix design rule check/layout versus schematic/antenna/electrical rule check/design for manufacturing violationsDevelop/modify design flows as needed to meet the overall design quality of results and chip integration requirementsBASIC QUALIFICATIONS:Bachelors degree in electrical engineering, computer engineering or computer science5+ years of ASIC top level tapeout and/or physical design flow development experiencePREFERRED SKILLS AND EXPERIENCE:Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)Experience in IP integration (e.g. memories, I/Os, analog IPs, SerDes, DDR etc.)In-depth knowledge of industry standard EDA tools, understand their capabilities and underlying algorithmsExperience with large SOC designs (>10M gates) with frequencies in excess of 1GHZStrong knowledge of deep sub-micron FinFET technology nodes (7nm and below) design problems and solutions (leakage power, signal integrity, etc.) multi-corner and multimode timing closure, process variations, physical verification methodology and tapeoutFamiliar with implementation or integration of design blocks using Verilog/System VerilogExperience with clock domain crossings, DFT/Scan/MBIST/LBIST/JTAG/Boundary-scan testing and understanding impacts on physical design flowExperience with high reliability design and implementationsExcellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environmentADDITIONAL REQUIREMENTS:Must be willing to travel when needed (typically



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