Sr. SOC Physical Design STA

3 weeks ago

Irvine, United States SpaceX Full time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. SOC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 1.5M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Develop/support automated block and full chip level advanced timing/noise signoff flows (with advanced and parametric on chip variation, and voltage drop aware STA)
  • Define block and full chip timing signoff criterion, methodology, constraints, modes and scenarios and close timing at multi-corner and multi-mode environments
  • Develop/support signoff STA timing/power optimization engineering change order flows and integrate them into physical design flow
  • Work with systems and architecture, SOC integration, verification, DFT, mixed signal, IP owners, synthesis, and place/route teams to address the design challenges in the context of timing sign-off
  • Generate block timing begets, clock and I/O context files
  • Debug and drive fixing of constraint correlation issues between top and block level
  • Develop clock network simulation and jitter analysis methodologies
  • Drive custom IP integration, custom timing check flow enablement and closure until tapeout
  • Guide full chip team to plan and build reference/special clock trees for minimal jitter and insertion delay
  • Develop and run block/full chip level noise analysis flows and drive the noise/signal integrity closure with block and full chip engineers
  • Work with voltage drop, architecture, package teams to understand voltage drops, guard banding requirements, voltage and library selection for signoff STA and noise analysis

BASIC QUALIFICATIONS:

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 5+ years of experience in static timing analysis and timing closure of high-performance SOC designs

PREFERRED SKILLS AND EXPERIENCE:

  • Full chip and block level STA tapeout experience, constraint generation and partitioning
  • Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations, voltage drop aware STA, and clock reconvergence pessimism removal
  • Experience in IP integration (e.g. memories, I/Os, Analog IPs, SerDes, DDR etc.)
  • Experience in industry standard STA and Noise/Signal integrity analysis tools
  • Experience in clock jitter simulation and analysis methodologies
  • Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on physical design and timing closure
  • Deep understanding of ASIC synthesis and physical design flows and methodologies
  • Experience with high reliability design and implementations
  • Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.)
  • Familiar with implementation or integration of design blocks using Verilog/System Verilog
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

  • Must be willing to travel when needed (typically

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