FPGA Verification Engineer
3 weeks ago
Job Description Job Description Company DescriptionArista Networks is a fast-growing company and an industry leader in the ethernet switch industry. Our switch systems have touched every corner of the market - from the data centers of the worlds largest cloud-computing companies, to your local universitys server room, and every application in between. We design virtually all of the hardware and software that goes into our products and its a badge we wear proudly. This wouldnt be possible without the likes of talented engineers who are given the opportunity to fully lead their own projects and the freedom to think outside the box. Whether you are an intern, a junior engineer or someone whos been around the block, one thing is for certain - you will leave your mark.**This position requires to be onsite in Santa Clara, CA**Job DescriptionWe are looking for a motivated individual to join our FPGA Design Team at our headquarters in Santa Clara, CA, in the heart of Silicon Valley. In this position, you will be responsible for designing test bench, simulating, and testing FPGA RTL code that forms the backbone of our next generation systems.Job Responsibilities:Create and maintain test benches in Verilog/SystemVerilogCreate BFM, RTL models for new and existing designsDevelop the verification test plans and test casesReview the design functional coverageConcepts and Skills:Data and control architectures of a modern ethernet switch, including chip IO interfaces such as Interlaken, Ethernet PHY/MAC, PCIe, SMBus, SPI, MDIO, JTAG, etc.Protocols using Ethernet, such as PTP, SFlow, POE, etc.Simulation software for FPGA functional verificationQualifications2-4 years of designing Verilog/SystemVerilog RTL codeProficient in design verification tools and languages (SystemVerilog, SVA, Modelsim, Perl, Python, Unix shell scripts)Experience in the chip level verification environment setups, code/functional coverage collectionMotivated, passionate, with sense of urgency and commitment to achieve the targeted goalsStrong scripting, debugging and problem solving skillsExcellent in-person, video, and written communication skillsAdditional InformationThe new hire base pay for this role has a salary range of $130,000 to $180,000. The actual salary offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and US location. The salary range provided reflects the base salary and in addition may also be eligible for discretionary Arista bonuses, commissions, equity, and benefits including medical, dental, vision, well-being, tax savings, and income protection.All your information will be kept confidential according to EEO guidelines.#J-18808-Ljbffr
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FPGA Verification Engineer
4 weeks ago
Santa Clara, United States Arista Full timeArista Networks is a fast-growing company and an industry leader in the ethernet switch industry. Our switch systems have touched every corner of the market - from the data centers of the world’s largest cloud-computing companies, to your local university’s server room, and every application in between. We design virtually all of the hardware and...
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FPGA Verification Engineer
4 weeks ago
Santa Clara, United States Arista Networks Full timeJob DescriptionJob DescriptionCompany DescriptionArista Networks is a fast-growing company and an industry leader in the ethernet switch industry. Our switch systems have touched every corner of the market - from the data centers of the world’s largest cloud-computing companies, to your local university’s server room, and every application in between. We...
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FPGA Verification Engineer
1 week ago
Santa Clara, CA, United States Arista Networks Full timeCompany DescriptionArista Networks is a fast-growing company and an industry leader in the ethernet switch industry. Our switch systems have touched every corner of the market - from the data centers of the world’s largest cloud-computing companies, to your local university’s server room, and every application in between. We design virtually all of the...
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Design Verification Engineer
3 days ago
Santa Clara, United States Ampcus Full timeRole: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: Mandatory JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans...
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Design Verification Engineer
3 weeks ago
Santa Clara, United States Mirafra Technologies Full timeLooking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...
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Design Verification Engineer
3 weeks ago
Santa Clara, United States Mirafra Technologies Full timeLooking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...
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Design Verification Engineer
3 weeks ago
Santa Clara, United States Mirafra Technologies Full timeLooking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...
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Design Verification Engineer
7 days ago
Santa Clara, United States Mirafra Technologies Full timeLooking to add DV Engineers in Irvine, San Diego and Santa Clara. Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip...
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Entry-Level/Junior FPGA Design Engineer
4 weeks ago
Santa Clara, United States XONE TECHNOLOGY, INC. Full timeJoina dynamic, motivated and passionate engineering team at a Silicon Valleystartup developing sophisticated communication products. XONE is lookingfor an entry- or junior-level engineer who will be responsible for implementingcomplex signal processing algorithms on state-of-the-art FPGA devicessuch as the XILINX Zynq SoC. Experience a unique professional...
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Santa Clara, United States PDDN Inc Full timeRole: Design Verification EngineerLocation: Santa Clara, CAInterview: Phone/SkypeJob Type: Contract Background check: MandatoryMeet and great: Mandatory UVM/OVM/SystemVerilog/Python/C/C++Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog...
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Senior CPU Verification Engineer
1 day ago
Santa Clara, United States NVIDIA Full timeWe are now looking for a Senior CPU Verification Engineer.We are currently seeking a Senior Verification Engineer with strong CPU and verification fundamentals to work in NVIDIA's CPU team. This position offers the opportunity to have real impact in a progressive, technology-focused company impacting product lines ranging from consumer graphics to...
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Senior Memory Controller Verification Engineer
4 weeks ago
Santa Clara, United States NVIDIA Full timeNVIDIA is seeking hardworking and creative Senior Memory Controller Verification Engineer for our Tegra SoCs! At Nvidia, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the...
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Verification Engineer
4 weeks ago
Santa Clara, California, United States Cynet Systems Inc Full timeJob Role Verification EngineerJob Type Contract Job Location Santa Clara CA (or) Job DescriptionVerification Engineer for Memory Controller Significant UVM SystemVerilog experience in complex test-benches Experience working with DRAM controller PHYs memory models is preferred Significant experience with general verification flows and metrics Excellent debug...
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Product Test Engineer
1 week ago
Santa Clara, United States Achronix Semiconductor Full timeAchronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further...
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Accelerator Verification Engineer
4 weeks ago
Santa Clara, United States CareerBuilder Full timeJOB TITLE: Accelerator Verification Engineer LOCATION: (US) Santa Clara CA , Austin TX, Portland OR, Fort Collins CO QUALIFICATIONS: Join a cutting-edge hardware startup in Silicon Valley as a Silicon Verification Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the...
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Verification Engineer
2 weeks ago
Santa Clara, United States ACL Digital Full timeJob Description : We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where they are. Develop test plans and test benches for module level verification ...
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ASIC Verification Engineer
1 month ago
Santa Clara, United States QData Full timeRequired Qualifications 4+ years’ experience required in verification. System Verilog /UVM experience (Mandatory). Good understanding of PCIe and Ethernet is needed. Engineer must have good understanding of complete verification life cycle (test plan test bench till coverage closure). Define SoC verification strategy. Good understanding of SoC life...
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ASIC Verification Engineer
1 month ago
Santa Clara, California, United States QData Full timeRequired Qualifications 4+ years' experience required in verification. System Verilog /UVM experience (Mandatory). Good understanding of PCIe and Ethernet is needed. Engineer must have good understanding of complete verification life cycle (test plan test bench till coverage closure). Define SoC verification strategy. Good understanding of SoC life cycle....
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Senior Verification Engineer
17 hours ago
Santa Clara, United States NVIDIA Full timeSenior Verification Engineer - Tegra page is loaded Senior Verification Engineer - Tegra Apply locations US, CA, Santa Clara time type Full time posted on Posted 2 Days Ago job requisition id JR1980777 We are now looking for a Senior Verification Engineer for our Tegra group! NVIDIA is seeking outstanding Senior Verification Engineers to verify the design...
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Senior Memory Controller Verification Engineer
1 month ago
Santa Clara, CA, United States NVIDIA Full timeNVIDIA is seeking hardworking and creative Senior Memory Controller Verification Engineer for our Tegra SoCs! At Nvidia, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the...