Design Verification Engineer

3 weeks ago


Austin, United States Mastech Digital Full time

Job Title: Design Verification Engineer

Location: Austin, TX

Position Details:

  • Define/plan/implement/execute functional verification strategy of complex System IP designs.
  • Develop feature-based test plans
  • Ability to delve into the details of Coherent fabric & LLC design.
  • Work with DV team and designers to build verification environments.
  • Develop UVM sequences, tests, scoreboards, monitors and checkers.
  • Write SVA assertions. Functional and Code coverage Closure.
  • Regression triaging and debug.
  • Agility to work on multiple tasks/projects.

Requirements

Skills And Qualifications Minimum requirements:

  • BS/MS/PhD (or equivalent experience)
  • 12+ years of relevant experience in Verification.
  • Experience with System Verilog and UVM.
  • Deep understanding of constrained randomization and the development of efficient test suites.
  • Proficient in a script language like Perl or Python.
  • Working knowledge of C++
  • Good knowledge of memory subsystem, including interconnect, last-level cache, coherency.
  • Familiarity of Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
  • Experience with Chip2Chip, Die2Die protocols like UCI-E, C2C preferred.
  • Good communication skills and ability & desire to work as a team player are a must.


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