Design Verification Engineer

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and...

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and...

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and...

JOB TITLE: Design Verification Engineer LOCATION: Austin, TX DURATION: 1 year PAY RANGE: $90 - $120/hr TOP SKILLS: • Current state-of-the-art testbench development such as UVM methodology • Experience in design verification with UVM and SystemVerilog is a MUST • 5-15 year's industry experience in a design verification role. COMPANY: Our client, a...

Summary: Meta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map...

JOB TITLE: Design Verification Engineer LOCATION: Austin, TX or San Jose, CA or San Diego, CA DURATION: 1 year PAY RANGE: $90 - $120/hr TOP SKILLS: • Current state-of-the-art testbench development such as UVM methodology • Experience in design verification with UVM and SystemVerilog is a MUST • 5-15 year's industry experience in a design verification...

JOB TITLE: Design Verification Engineer LOCATION: Austin, TX or San Jose, CA or San Diego, CA DURATION: 1 year PAY RANGE: $90 - $120/hr TOP SKILLS: • Current state-of-the-art testbench development such as UVM methodology • Experience in design verification with UVM and SystemVerilog is a MUST • 5-15 year's industry experience in a design verification...

Job Title: Design Verification Engineer Duration: FTE / Permanent Hiring Location: Austin TX or San Jose CA (Need Local Onsite)Description: Description As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities •Triage regression failures and make...

Design Verification Engineer – Competitive Salary – Austin, Tx OR Santa Clara, California I’m working with an exciting RISC-V Start Up who are keen to onboard full-time SOC Verification Engineers. I’m looking for individuals with a range of experience levels. Whether you’re a beginner or a seasoned professional, I’d love to chat!What you'll do:...

Design Verification Engineer – Competitive Salary – Austin, Tx OR Santa Clara, California I’m working with an exciting RISC-V Start Up who are keen to onboard full-time SOC Verification Engineers. I’m looking for individuals with a range of experience levels. Whether you’re a beginner or a seasoned professional, I’d love to chat!What you'll do:...

Design Verification Engineer – Competitive Salary – Austin, Tx OR Santa Clara, California I’m working with an exciting RISC-V Start Up who are keen to onboard full-time SOC Verification Engineers. I’m looking for individuals with a range of experience levels. Whether you’re a beginner or a seasoned professional, I’d love to chat!What you'll do:...

Design Verification Engineer – Competitive Salary – Austin, Tx OR Santa Clara, California I’m working with an exciting RISC-V Start Up who are keen to onboard full-time SOC Verification Engineers. I’m looking for individuals with a range of experience levels. Whether you’re a beginner or a seasoned professional, I’d love to chat!What you'll do:...

Design Verification Engineer – Competitive Salary – Austin, Tx OR Santa Clara, California I’m working with an exciting RISC-V Start Up who are keen to onboard full-time SOC Verification Engineers. I’m looking for individuals with a range of experience levels. Whether you’re a beginner or a seasoned professional, I’d love to chat!What you'll do:...

DescriptionDesign Verification Engineer12 Months contract with possibility of extensionAustin, TX (Hybrid 3 - 4 days in office)As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug...

DescriptionDesign Verification Engineer12 Months contract with possibility of extensionAustin, TX (Hybrid 3 - 4 days in office)As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug...

DescriptionDesign Verification Engineer12 Months contract with possibility of extensionAustin, TX (Hybrid 3 - 4 days in office)As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug...

Job Title: Design Verification Engineer #368877Duration: 12+ months (Possible Extension-Long Term Project)Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite)DescriptionAs a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. ResponsibilitiesTriage regression...

Position: Design Verification Engineer Location: Austin, TX (Onsite) Duration: Long-term Position Overview: 12+ years of relevant experience in Verification. Experience with System Verilog and UVM. Deep understanding of constrained randomization and the development of efficient test suites. Work with DV team and designers to build verification...

Role: Design Verification EngineerLocation: AUSTIN , TX OnsiteDuration :10+ Months Requirements:8+ years of experience in UVM based verification.System Verilog assertions experienceFamiliarity with C/C++ model integration in verification environmentsDebug skills at IP and subsystem level.Good to have:GLS verification knowledgeLow power UPF verificationARM...

Position: Design Verification Engineer Location: Austin, TX (Onsite/Hybrid) Position Overview: 5+ years of relevant experience in Design Verification. Experience with System Verilog and UVM is a must. Strong experience in testbench development such as UVM methodology. Knowledge of GPU, experience with Shader, Texture, or Memory System a plus. Education:...