Design Verification Engineer

Senior Design Verification EngineerSanta Clara CA/ Remote is fine5 Positions JOB DESCRIPTIONAt least 7+of experience in Design VerificationStrong UVM, SystemVerilog, VerilogScripting in Perl or Python programming skills.Good experience in protocols such as AMBA, AHB, AXI, PCI Express etc.

Senior Design Verification EngineerSanta Clara CA/ Remote is fine5 Positions JOB DESCRIPTIONAt least 7+of experience in Design VerificationStrong UVM, SystemVerilog, VerilogScripting in Perl or Python programming skills.Good experience in protocols such as AMBA, AHB, AXI, PCI Express etc.

Senior Design Verification EngineerSanta Clara CA/ Remote is fine5 Positions JOB DESCRIPTIONAt least 7+of experience in Design VerificationStrong UVM, SystemVerilog, VerilogScripting in Perl or Python programming skills.Good experience in protocols such as AMBA, AHB, AXI, PCI Express etc.

Role: Design Verification EngineerLocation: Santa Clara, CA (onsite)Duration: 12 contractJob Description: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new...

Role: Design Verification EngineerLocation: Santa Clara, CA (onsite)Duration: 12 contractJob Description: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new...

Role: Design Verification EngineerLocation: Santa Clara, CA (onsite)Duration: 12 contractJob Description: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new...

Title: Design Verification Engineer Duration: Full TimeLocation: Santa Clara, CADescription :Experience in pre-silicon RTL Verification /IP Verification / SOC verification. Experience in verification domain (block-level, chip-level, and system-level verification) and verification methodologies. Working knowledge of System Verilog and UVM. Working Knowledge...

Duration:12+ MonthsPosition Description• We are seeking seasoned verification lead with expertise or significant interest in IO/PHY verification.• You have had significant success driving IP verification, UVM and SystemVerilog.• This senior role will stretch you as you lead DV teams in new directions, network with our world-class design/DV teams.THE...

Astera Labs is a global leader in innovative connectivity solutions that unlock the full potential of AI and cloud infrastructure.Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a scalable and customizable...

Our client in the technology industry is seeking a Design Verification Engineer - Specialized to join their team. As a Design Verification Engineer - Specialized, you will be part of the Design Verification team supporting various projects. The ideal candidate will have excellent communication and presentation skills, demonstrated through technical...

Our client in the technology industry is seeking a Design Verification Engineer - Specialized to join their team. As a Design Verification Engineer - Specialized, you will be part of the Design Verification team supporting various projects. The ideal candidate will have excellent communication and presentation skills, demonstrated through technical...

Job Title: Verification Engineer (AXI)Location: Santa Clara, CA OR Austin, TXSalary Range: $80-90/hr on W2Job Type: Full-timeCompany Overview:HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. Our technology products and services are built on four decades of innovation, with...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture...

We are looking for Senior Design Verification Engineers.Do you have a flair for being a code breaker and the ability to develop hybrid mechanisms for the verification of complex ASICs? Experience with System Verilog, C, C++, Python, or other scripting languages. Using your coding and problem-solving skills, you will contribute to the functional verification...

We are looking for Senior Design Verification Engineers.Do you have a flair for being a code breaker and the ability to develop hybrid mechanisms for the verification of complex ASICs? Experience with System Verilog, C, C++, Python, or other scripting languages. Using your coding and problem-solving skills, you will contribute to the functional verification...

Our client in the technology industry is seeking a Design Verification Engineer - Specialized to join their team. As a Design Verification Engineer - Specialized, you will be part of the Design Verification team supporting various projects. The ideal candidate will have excellent communication and presentation skills, demonstrated through technical...

We are seeking a highly skilled Senior Verification Engineer to join our CPU Verification Team. As a member of this team, you will be responsible for a portion of the Design Verification, focusing on tasks such as testbench/scoreboard/stimulus development, regression debug, and coverage closure, supporting design, implementation, and system level...

Job DescriptionSkills Required:-Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C testsIntegration/development of C tests/Application Programming Interface (“APIs”) and software build flowIntegration of UVM testbenchesTest development and debug, including without limitation tests for functionality, power,...

Job DescriptionSkills Required:-Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C testsIntegration/development of C tests/Application Programming Interface (“APIs”) and software build flowIntegration of UVM testbenchesTest development and debug, including without limitation tests for functionality, power,...