Design Verification Engineer
2 weeks ago
We are seeking a highly skilled Design Verification Engineer to join our advanced semiconductor design team in the Bay Area. The ideal candidate will have a strong background in SystemVerilog, UVM, and C/C++ programming, and be capable of driving complex verification tasks independently. This is an exciting opportunity to work on next-generation SoC and IP designs in a fast-paced, innovation-driven environment. Key Responsibilities Develop, enhance, and execute verification plans for complex SoC/IP blocks. Design and maintain SystemVerilog-based testbenches using UVM methodology. Develop C/C++ models, transactors, or test components to support mixed-language simulation environments. Perform functional and coverage-based verification, ensuring design correctness and completeness. Work closely with RTL designers and architects to define verification strategies and close verification coverage. Debug issues across simulation environments and regression runs using industry-standard tools. Automate verification flows and contribute to continuous process improvement. Must-Have Skills & Experience 3–10 years of experience in Design Verification. Strong proficiency in SystemVerilog for testbench development and assertions. Hands‑on experience with UVM methodology (environment creation, sequences, and scoreboards). Solid programming experience in C and C++ for model development, DPI integration, or testbench components. Strong understanding of digital design concepts, SoC architecture, and verification methodologies. Expertise with industry‑standard simulation tools (e.g., VCS, QuestaSim, Incisive, Xcelium). Excellent analytical, debugging, and communication skills. Proven ability to work independently and deliver high-quality verification deliverables on schedule. Preferred Qualifications Experience with coverage‑driven verification and assertion‑based verification. Familiarity with Python, Perl, or TCL scripting for automation. Understanding of standard bus protocols such as AXI, AHB, PCIe, or Ethernet. Exposure to low‑power verification and formal verification techniques. Candidates must currently reside in the U.S. (Bay Area preferred) with valid work authorization. Immediate joiners or candidates available within 2 weeks will be prioritized. Why Join Us Be part of a world‑class verification team building cutting‑edge semiconductor solutions. Opportunity to work with industry experts and leading EDA tools. Competitive compensation and flexible engagement structure. #J-18808-Ljbffr
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Design Verification Engineer
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San Francisco, CA, United States Eximietas Design Full timeEximietas Design is a leading technology consulting and solutions development firm specializing in VLSI, Cloud Computing, Cyber Security, and AI/ML. Our engineering leadership team brings decades of experience from top-tier semiconductor and technology companies. With a deep commitment to innovation and excellence, we deliver cuttingedge solutions that help...
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Design Verification Engineer
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San Francisco, United States Eridu AI Full timeJoin to apply for the Design Verification Engineer role at Eridu AIJoin to apply for the Design Verification Engineer role at Eridu AIGet AI-powered advice on this job and more exclusive features.This range is provided by Eridu AI. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.Base pay...
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Design Verification Engineer
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San Francisco, United States EDA CAREERS, (Technology Futures Inc). Full timeGet AI-powered advice on this job and more exclusive features.Direct message the job poster from EDA CAREERS, (Technology Futures Inc).President at EDA-CAREERS and TECHNOLOGY FUTURES Inc.YOU MUST HAVE WORKING KNOWLEDGE OF EDA tools and Semiconductors!PLEASE HAVE EDA/SEMICONDUCTOR EXPERIENCE WHEN APPLYING!My client is a promising, innovative, well-funded...
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Design Verification Engineer
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San Francisco, CA, United States Kasmo Global Full timeTitle : Design Verification Engineer Location : San Jose, C s a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug...
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Design Verification Engineering
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San Francisco, CA, United States Eridu AI Full timeJoin to apply for the Design Verification Engineer role at Eridu AI Join to apply for the Design Verification Engineer role at Eridu AI Get AI-powered advice on this job and more exclusive features. This range is provided by Eridu AI. Eridu AI is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate training...
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Design Verification Engineering
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San Francisco, CA, United States Amazon Full timeAs a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. You will participate in the design verification and bring‑up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. ...
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Design Verification Engineer
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San Francisco, United States Apple Full timeRole Number: 200627018-3401 Summary At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and...
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Design Verification Engineer
4 days ago
San Francisco, United States Apple Full time**Role Number:** 200627151-3401 **Summary** At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare...
